by George Riley, HyComp Inc.
by Don Moore, President, Semiconductor Equipment Corporation
Solid State Technology, 1999
|For many microelectronics manufacturers, it is more cost – effective to apply flip chip interconnects for prototyping, production start – up, and low – volume production applications on singulated die, rather than using the conventional approach of solder bumping wafers. This was certainly the case for HyComp, a manufacturer of hybrid circuits.
At HyComp, we saw the first inkling of flip chip interconnect being practical for smaller volume production with the application of conductive adhesives, instead of solder, to flip chip connections. This new technique offered a simpler, less capital – intensive approach to flip chip , and opened a path to denser, faster hybrid circuits and multichip modules manufactured in quantities of tens of thousands of units.
In the mid – 1990s, after completing some preliminary work on adhesive flip chip reliability , HyComp received DARPA funding to examine the feasibility of flip chip in these lower – volume applications and to set up a prototype low – volume flip chip production facility.
Looking at various new bumping approaches that were being applied to flip chip interconnect, we believe that the use of wire bonding to create metal bumps (i.e., gold wire “stud bumping”) was compatible with conductive adhesive attachment and offered a practical die – based solution for low – volume flip – chip production.
Stud Bumping Single Chips
The process is further enhanced by flattening the stud bumps on the IC bond pads (Fig. 1b); this is done by applying pressure against a smooth surface or striking the studs with an appropriate wire bonder tool. Flattening the remaining wire tails into balls creates a smooth top surface with improved bump coplanarity. Making bump heights uniform optimizes bump contact with the substrate when the chip is flipped and mounted. In addition, we have found that shaping the studs helps to retain more conductive adhesive at the bump – to – substrate interface during the subsequent flip – chip assembly process.
Most ball – bonding equipment today can perform the above procedures; we used a Hughes Model 2460. This bonder can readily place stud bumps on bond pads with dimensions <100µm² and center – to – center pitches <150µm. These dimensions are typical of common analog, logic, and memory ICs. Bonder fixturing can be readily modified to hold and stud bump single IC chips.
Adhesive Application Choices
Our use of SEC’s Model 410 flip – chip bonder provided the control over planarity, position, and motion that dipped adhesive requires. We used this system to vacuum pick face – down die out of a waffle pack and dip them into a dish of conductive adhesive on a micrometer – leveled pedestal on the bonder’s workstage. Prior to dipping, the conductive adhesive is spread evenly with a razor edge blade; trial – and – error tests determined the proper adhesive thickness to transfer to the bumps without bridging the adhesive across bumps.
The dipping process is initiated manually, with the operator using the system’s vision system simultaneously to view the bumps and the adhesive, then is completed automatically. Figure 2 shows a flattened bump after dipping.
Adhesive can also be applied via a precision stenciling system (e.g., the MPM Model SPM0). Our stencil thickness ranged from 25 to 100µm and stencil openings ranged from 37 to 100µm, to match various bond pad sizes and pitches.
Both dipping and stenciling resulted in satisfactory electrical performance. Stenciling is faster than dipping, but stenciling yields decrease rapidly for pitches <150µm. In addition, a precise stenciler is the more costly equipment approach. On the other hand, just by the nature of the dipping process, less conductive adhesive ends up on the contact surface. Dipping also requires more precise control of the quantity of adhesive transferred to the chip bumps to achieve a satisfactory electrical and mechanical joint. Both dipping and stenciling can be automated for higher throughput.
An alternative process to isotropic conductive adhesive assembly followed by nonconductive underfill is to use only a non – conductive adhesive in assembly . For this method, a die bonder applies and maintains compressive pressure on the contacts while the nonconductive adhesive is heat – cured, on the die bonder, to fix the flipped die in place. One advantage with this method is that the nonconductive adhesive also serves as underfill, eliminating subsequent underfill injection and curing steps. A disadvantage is that continuing to hold the die under pressure during curing lowers the throughout of the bonder.
We found that success in the nonconductive adhesive assembly of single chips puts stringent requirements on temperature and pressure capability of the flip chip die bonder. For example, the workstage should be capable of being heated to 350°C with the die tool heated to 200°C. Temperature profiles and bond loads need to be computer – controlled to achieve critical operating precision and repeatability. A closed loop bond load range of 100 – 2000g or higher, depending on the number of bumps, should be available to allow for handling a variety of chips and substrate materials.
Placing, Attaching Chips
With our aligner – bonder, the bumped die is held in a vacuum collet while the substrate is placed on the traversing workstation and then moved into approximate position under the chip. A beam splitter allows the operator to view simultaneously the chip stud bumps and substrate bump pads superimposed on a monitor while making fine adjustments.
Adequate lighting of both the flip – chip bumps and substrate is crucial to rapid, precise alignment. This can best be achieved by a system that has separate, adjustable illuminators, one for the chip bumps and one for the bond pads. Also crucial, particularly when bonding small flip chips, are capabilities for fine motorized movements of the workstage, precise incremental movements of the viewer, and a wide range of zooming with the camera lens. These capabilities are particularly important for process development and prototyping, when a wide variety of chips and substrate materials may be used.
In our process, once the bumps and pads are in alignment, the operator initiates the automatic placement cycle that retracts the viewer and places the chip gently onto the substrate bond pads under a pre – programmed load. The load should be just enough to cause the chip to seat properly on the bond pads. The assembly is then removed from the aligner – bonder and the conductive adhesive is oven – cured to specification (Figure 3).
Figure 4 shows an IC assembled to a glass substrate, as viewed through the substrate. The gold tracks, on the far side of the glass, connect through stud bumps to the IC bond pads. A dark ring of conductive adhesive surrounds each connecting stud. The usual underfill was omitted to permit photography.
Testing and Underfulling
The assembly process is completed by filling the remaining spaces between the chip and substrate with a nonconductive underfill adhesive. This adhesive provides mechanical strength and robustness, while sealing conductive connections against moisture and contaminants. The thermal expansion of the underfill material is chosen to compensate for differential thermal expansion coefficients of the chip and substrate. The underfill locks chip and substrate together during temperature excursions.
For this process development, underfill (in our case Alpha Metals EL – 18) is syringe – dispensed in a dot or line at one edge of the chip. Automated dispensing systems for underfill are available from several manufacturers. The substrate is then heated to 50°C until capillary action draws the underfill into the chip – substrate gap. The underfill is oven – cured to the manufacturer’s recommendation.
Process development steps included evaluation of the mechanical and electrical performance of each conductive adhesive assembly. We also studied the functionality and electrical characteristics of the gold stud bumps placed on standard aluminum IC bond pads. We tested stud bump uniformity over the high pad counts of RAM chips and also the dipped adhesive uniformity over a large area for the array assembly. Altogether, we assembled and tested more than 1000 standard IC chip and test devices, containing more than 15,000 flip – chip connections.
One series of tests focused on the repeatability and yield of the flip – chip connections. Success was measured in terms of repeatable high – yield interconnects showing little electrical variation from bump to bump and chip to chip. We used probe cards, fabricated for each type of chip and equipped with tungsten probes, on a computer – based probing station to get two – wire resistance readings through each stud bump connection.
We measured a total of 170 connections/substrate in each of eight test runs, measuring each connection’s resistance twice: once after curing the conductive adhesive but before underfilling, and again after underfilling and curing the underfill. This gave a total of 340 resistance measurements /group of 10 chips. We calculated the average across all connections on each test chip and the average of connections for each contact position across all test chips of that type. Standard deviations of the averaged data flagged any discrepancies for further study.
The average resistance over the 10 devices in each test run before under filling ranged from 0.41 – 0.45. After underfilling, the range was from 0.42 – 0.46d. The range of corresponding standard deviations was 0.02 – 0.04 and 0.03 – 0.05. Such variations over the 1360 measurement are well within what can be expected, given the small differences in contact alignment and adhesive coating. These two wire readings do not give values of contact resistance alone, since probe and track resistance is included. To establish contact resistance values, we took manual four – point Kelvin probe measurements. The values resulting from such measurements generally are less than 10% of those from two – wire automated resistance measurements and are considered with other reported conductive adhesive measurements .
|Reprinted from the October 1999 edition of Solid State Technology
Copyright 1999 by PennWel